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hm62w8512b series 4 m sram (512-kword 8-bit) ade-203-904e (z) rev. 4.0 oct. 20, 1999 description the hitachi hm62w8512b is a 4-mbit static ram organized 512-kword 8-bit. it realizes higher density, higher performance and low power consumption by employing 0.35 m hi-cmos process technology. the device, packaged in a 525-mil sop (foot print pitch width) or 400-mil tsop type ii is available for high density mounting. the hm62w8512b is suitable for battery backup system. features single 3.3 v supply: 3.3 v ?0.3 v access time: 55/70 ns (max) power dissipation ? active: 16.5 mw/mhz (typ) ? standby: 3.3 ? (typ) completely static memory. no clock or timing strobe required equal access and cycle times common data input and output: three state output directly lv-ttl compatible: all inputs and outputs battery backup operation
hm62w8512b series 2 ordering information type no. access time package hm62w8512blfp-5 hm62w8512blfp-7 55 ns 70 ns 525-mil 32-pin plastic sop (fp-32d) hm62w8512blfp-5sl hm62w8512blfp-7sl 55 ns 70 ns hm62w8512blfp-5ul hm62w8512blfp-7ul 55 ns 70 ns hm62w8512bltt-5 hm62w8512bltt-7 55 ns 70 ns 400-mil 32-pin plastic tsop ii (ttp-32d) hm62w8512bltt-5sl hm62w8512bltt-7sl 55 ns 70 ns hm62w8512bltt-5ul hm62w8512bltt-7ul 55 ns 70 ns hm62w8512blrr-5 hm62w8512blrr-7 55 ns 70 ns 400-mil 32-pin plastic tsop ii reverse (ttp-32dr) hm62w8512blrr-5sl hm62w8512blrr-7sl 55 ns 70 ns hm62w8512blrr-5ul hm62w8512blrr-7ul 55 ns 70 ns
hm62w8512b series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v cc a15 a17 we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v cc a15 a17 we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v cc a15 a17 we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 (top view) hm62w8512blfp series hm62w8512bltt series hm62w8512blrr series (top view) (top view) pin description pin name function a0 to a18 address input i/o0 to i/o7 data input/output cs chip select oe output enable we write enable v cc power supply v ss ground
hm62w8512b series 4 block diagram i/o0 i/o7 cs we oe a13 a17a15 a8 a10 a11 v v cc ss row decoder memory matrix 1,024 4,096 column i/o column decoder input data control timing pulse generator read/write control a5 a9 a4 a18 a16 a1 a0 a2 a12 a14 a3 a7 a6
hm62w8512b series 5 function table we cs oe mode v cc current dout pin ref. cycle h not selected i sb , i sb1 high-z h l h output disable i cc high-z h l l read i cc dout read cycle l l h write i cc din write cycle (1) l l l write i cc din write cycle (2) note: : h or l absolute maximum ratings parameter symbol value unit power supply voltage v cc ?.5 to +4.6 v voltage on any pin relative to v ss v t ?.5* 1 to v cc + 0.5* 2 v power dissipation p t 1.0 w operating temperature topr ?0 to +70 c storage temperature tstg ?5 to +125 c storage temperature under bias tbias ?0 to +85 c notes: 1. ?.0 v for pulse half-width 30 ns 2. maximum voltage is 4.6 v recommended dc operating conditions (ta = ?0 to +70c) parameter symbol min typ max unit supply voltage v cc 3.0 3.3 3.6 v v ss 000v input high voltage v ih 2.0 v cc + 0.3 v input low voltage v il ?.3* 1 0.8 v note: 1. ?.0 v for pulse half-width 30 ns
hm62w8512b series 6 dc characteristics (ta = ?0 to +70c, v cc = 3.3 v ?0.3 v, v ss = 0 v) parameter symbol min typ* 1 max unit test conditions input leakage current |i li | 1 m a vin = v ss to v cc output leakage current |i lo | 1 m a cs = v ih or oe = v ih or we = v il , v i/o = v ss to v cc operating power supply current: dc i cc 10 ma cs = v il , others = v ih /v il , i i/o = 0 ma operating power supply current hm62w8512b-5 i cc1 45 ma min cycle, duty = 100% cs = v il , others = v ih /v il i i/o = 0 ma hm62w8512b-7 i cc1 40 ma operating power supply current i cc2 5 10 ma cycle time = 1 m s, duty = 100% i i/o = 0 ma, cs 0.2 v v ih 3 v cc ?0.2 v, v il 0.2 v standby power supply current: dc i sb 0.1 0.3 ma cs = v ih standby power supply current (1): dc i sb1 ?* 2 40* 2 m a vin 3 0 v, cs 3 v cc ?0.2 v ?* 3 20* 3 m a ?* 4 5* 4 m a output low voltage v ol 0.4 v i ol = 2.0 ma 0.2 v i ol = 100 m a output high voltage v oh v cc ?0.2 v i oh = ?00 m a 2.4 v i oh = ?.0 ma notes: 1. typical values are at v cc = 3.3 v, ta = +25 c and specified loading, and not guaranteed. 2. this characteristics is guaranteed only for l version. 3. this characteristics is guaranteed only for l-sl version. 4. this characteristics is guaranteed only for l-ul version. capacitance (ta = +25c, f = 1 mhz) parameter symbol typ max unit test conditions input capacitance* 1 cin 8 pf vin = 0 v input/output capacitance* 1 c i/o ?0pfv i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
hm62w8512b series 7 ac characteristics (ta = ?0 to +70c, v cc = 3.3 v ?.3 v, unless otherwise noted.) test conditions input pulse levels: 0.4 v to 2.4 v input rise and fall time: 5 ns input timing reference levels: 1.4 v output timing reference level: 0.8 v/2.0 v output load (including scope & jig) dout 500 1.4 v 50 pf w read cycle hm62w8512b -5 -7 parameter symbol min max min max unit notes read cycle time t rc 55 70 ns address access time t aa 55 70 ns chip select access time t co 55 70 ns output enable to output valid t oe 25 35 ns chip selection to output in low-z t lz 10 10 ns 2 output enable to output in low-z t olz 55ns2 chip deselection to output in high-z t hz 0 20 0 30 ns 1, 2 output disable to output in high-z t ohz 0 20 0 30 ns 1, 2 output hold from address change t oh 10 10 ns
hm62w8512b series 8 write cycle hm62w8512b -5 -7 parameter symbol min max min max unit notes write cycle time t wc 55 70 ns chip selection to end of write t cw 50 60 ns 4 address setup time t as 00ns5 address valid to end of write t aw 50 60 ns write pulse width t wp 40 50 ns 3, 12 write recovery time t wr 00ns6 we to output in high-z t whz 0 20 0 30 ns 1, 2, 7 data to write time overlap t dw 25 30 ns data hold from write time t dh 00ns output active from output in high-z t ow 55ns2 output disable to output in high-z t ohz 0 20 0 30 ns 1, 2, 7 notes: 1. t hz , t ohz and t whz are defined as the time at which the outputs achieve the open circuit?onditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. a write occurs during the overlap (t wp ) of a low cs and a low we . a write begins at the later transition of cs going low or we going low. a write ends at the earlier transition of cs going high or we going high. t wp is measured from the beginning of write to the end of write. 4. t cw is measured from cs going low to the end of write. 5. t as is measured from the address valid to the beginning of write. 6. t wr is measured from the earlier of we or cs going high to the end of write cycle. 7. during this period, i/o pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. if the cs low transition occurs simultaneously with the we low transition or after the we transition, the output remain in a high impedance state. 9. dout is the same phase of the write data of this write cycle. 10. dout is the read data of next address. 11. if cs is low during this period, i/o pins are in the output state. therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. in the write cycle with oe low fixed, t wp must satisfy the following equation to avoid a problem of data bus contention. t wp 3 t dw min + t whz max
hm62w8512b series 9 timing waveforms read timing waveform ( we = v ih ) t aa t co t rc t lz t oe t olz t hz t ohz valid data address cs oe dout t oh
hm62w8512b series 10 write timing waveform (1) ( oe clock) t wc t cw t wp t as t ohz t dw t dh t aw t wr *8 address oe cs we dout din valid data
hm62w8512b series 11 write timing waveform (2) ( oe low fixed) address cs we dout din t wc t cw t wr t aw t wp t as t whz t ow t oh t dw t dh *11 *9 *10 *8 valid data
hm62w8512b series 12 low v cc data retention characteristics (ta = ?0 to +70c) parameter symbol min typ max unit test conditions* 4 v cc for data retention v dr 2v cs 3 v cc ?0.2 v, vin 3 0 v data retention current i ccdr 0.8* 5 20* 1 m av cc = 3.0 v, vin 3 0 v cs 3 v cc ?0.2 v 0.8* 5 10* 2 m a 0.8* 5 2* 3 m a chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r t rc * 6 ns notes: 1. for l-version and 10 m a (max.) at ta = ?0 to +40 c. 2. for l-sl-version and 3 m a (max.) at ta = ?0 to +40 c. 3. for l-ul-version and 2 m a (max.) at ta = ?0 to +40 c. 4. cs controls address buffer, we buffer, oe buffer, and din buffer. in data retention mode, vin levels (address, we , oe , i/o) can be in the high impedance state. 5. typical values are at v cc = 3.0 v, ta = +25 c and specified loading, and not guaranteed. 6. t rc = read cycle time. low v cc data retention timing waveform ( cs controlled) cc v 3.0 v 2.0 v 0 v cs t cdr t r cs v ?0.2 v cc 3 dr v data retention mode
hm62w8512b series 13 package dimensions hm62w8512blfp series (fp-32d) hitachi code jedec eiaj weight (reference value) fp-32d conforms 1.3 g unit: mm *dimension including the plating thickness base material dimension 0.15 m *0.40 0.08 20.45 1.00 max 1.27 11.30 1.42 3.00 max *0.22 0.05 20.95 max 32 17 1 16 0 ?8 0.80 0.20 14.14 0.30 0.10 0.38 0.06 + 0.12 ?0.10 0.15 0.20 0.04
hm62w8512b series 14 package dimensions (cont.) hm62w8512bltt series (ttp-32d ) hitachi code jedec eiaj weight (reference value) ttp-32d conforms 0.51 g unit: mm *dimension including the plating thickness base material dimension 1.27 0.21 m *0.42 0.08 0.10 10.16 20.95 21.35 max 17 16 32 1 1.20 max 0 ?5 0.13 0.05 *0.17 0.05 11.76 0.20 0.50 0.10 1.15 max 0.80 0.40 0.06 0.125 0.04
hm62w8512b series 15 package dimensions (cont.) hm62w8512blrr series (ttp-32dr) hitachi code jedec eiaj weight (reference value) ttp-32dr conforms 0.51 g unit: mm *dimension including the plating thickness base material dimension 1.27 0.21 m *0.42 0.08 0.10 10.16 20.95 21.35 max 16 17 1 32 1.20 max 0 ?5 0.13 0.05 *0.17 0.05 11.76 0.20 0.50 0.10 1.15 max 0.80 0.40 0.06 0.125 0.04
hm62w8512b series 16 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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